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Cross Trigger Interface15.1 About the CTIThe CTI enables the debug logic, ETM, and PMU, to interact with each other and withother CoreSight components. This is called cross triggering. For example, you canconfigure the CTI to generate an interrupt when the ETM trigger event occurs.The CTI is connected to a number of trigger inputs and trigger outputs. You can connecteach trigger input to one or more trigger outputs. Figure 15-1 shows the debug systemcomponents and the available trigger inputs and trigger outputs.Cortex-A8nPMUIRQPMUPMUEXTIN[1:0]nCTIIRQPMUeventsDebugCOMMRXCOMMTXEDBGRQDBGTRIGGERDBGRESTARTCTIEXTIN[3:0]ETMEXTOUT[1:0]TRIGGERFigure 15-1 Debug system componentsThe CTI also implements a synchronous channel interface as defined in the CoreSightArchitecture Specification for communication with other CoreSight components.15.1.1 How the CTI worksThe CTI connects trigger inputs to trigger outputs using four channels. The followingcan cause a channel event:• A trigger input event, if you have configured the channel for the trigger inputusing the CTIINEN registers. See Trigger inputs and outputs on page 15-6 forinformation on trigger inputs and outputs that are available to the CTI.• An application trigger, using the CTIAPPSET, CTIAPPCLEAR, andCTIAPPPULSE registers.15-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E
Cross Trigger Interface• An input event on the channel interface.A channel event can cause the following to occur:• A trigger output event, if you have configured the channel for the trigger outputusing the CTIOUTEN registers. See Trigger inputs and outputs on page 15-6 forinformation on trigger inputs and outputs that are available to the CTI.• An output event on the channel interface, unless the channel interface output forthat channel has been disabled using the CTICHGATE Register.Figure 15-2 on page 15-4 shows the connections to the channels.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 15-3
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Cortex -A8Revision: r2p2Technical R
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Product StatusThe information in th
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ContentsCortex-A8 Technical Referen
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Contents7.8 Parity detection ......
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ContentsA.2 ATB interface .........
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List of TablesCortex-A8 Technical R
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List of TablesTable 3-103 Results o
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List of TablesTable 12-1 Access to
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List of TablesTable 15-3 CTI regist
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List of Tablesxx Copyright © 2006-
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List of FiguresFigure 3-10 Memory M
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List of FiguresFigure 10-13 Retenti
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List of FiguresFigure 15-16 CTI Cha
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PrefaceAbout this manualThis is the
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PrefaceChapter 16 Instruction Cycle
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PrefacePrefix CPrefix HPrefix nPref
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the processor
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Introduction1.3 Components of the p
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Introduction1.3.4 Load/storeThe loa
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Introduction1.4 External interfaces
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Introduction1.6 Power managementThe
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Introduction1.8 Product revisionsTh
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Introduction1-14 Copyright © 2006-
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Programmer’s Model• Hardware co
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Programmer’s Model2.2 Thumb-2 ins
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Programmer’s Model2.3 ThumbEE ins
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Programmer’s ModelThumbEE Handler
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Programmer’s Model2.4 Jazelle Ext
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Programmer’s Model— the registe
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Programmer’s ModelNonsecureSecure
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Programmer’s Model2.7 VFPv3 archi
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Programmer’s Model2.9 Data typesT
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Programmer’s ModelBitHigher addre
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Programmer’s Model2.12 Operating
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Programmer’s ModelIn privileged m
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Programmer’s Model16 generalpurpo
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Programmer’s ModelIn ARM state, y
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Programmer’s Model2.14.5 The GE[3
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Programmer’s ModelT bitThe T bit
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Programmer’s ModelOnly secure pri
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Programmer’s Model2.15.2 Leaving
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Programmer’s ModelAn internal or
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Programmer’s ModelImprecise data
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
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Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.1.6 Sys
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System Control Coprocessor3.2.20 c0
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System Control Coprocessora. An ent
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System Control CoprocessorThe Auxil
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System Control CoprocessorVA to PA
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System Control CoprocessorInvalidat
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System Control CoprocessorThe PMNC
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System Control CoprocessorCWhen wri
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System Control Coprocessorb. The EN
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System Control Coprocessor• acces
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System Control CoprocessorYou can c
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System Control CoprocessorTo access
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System Control CoprocessorTo access
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System Control CoprocessorThe PLE I
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System Control CoprocessorLDR R1, =
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System Control CoprocessorL1 Data 0
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System Control CoprocessorInstructi
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System Control CoprocessorParity/EC
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System Control CoprocessorL2 parity
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System Control CoprocessorThe L2 da
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Chapter 4Unaligned Data and Mixed-e
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Unaligned Data and Mixed-endian Dat
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Unaligned Data and Mixed-endian Dat
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Chapter 5Program Flow PredictionThi
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Program Flow Prediction5.2 Predicte
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Program Flow Prediction5.2.1 Return
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Program Flow Prediction5.4 Guidelin
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Program Flow Prediction5.6 Operatin
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Chapter 6Memory Management UnitThis
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Memory Management Unit6.2 Memory ac
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Memory Management Unit6.4 MMU inter
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Memory Management Unit6.6 TLB lockd
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Chapter 7Level 1 Memory SystemThis
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Level 1 Memory System7.2 Cache orga
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Level 1 Memory System7.3 Memory att
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Level 1 Memory SystemTable 7-1 Memo
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Level 1 Memory System7.5 Data cache
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Level 1 Memory SystemAn exception t
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Level 1 Memory System7.8 Parity det
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Chapter 8Level 2 Memory SystemThis
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Level 2 Memory System8.2 Cache orga
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Level 2 Memory System8.3 Enabling a
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Level 2 Memory SystemControl Regist
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Level 2 Memory System8.5 Synchroniz
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Chapter 9External Memory InterfaceT
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External Memory Interfaceto the wri
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External Memory InterfaceTable 9-2
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External Memory Interface9.3 AXI in
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External Memory InterfaceBWBCNoTTSS
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Chapter 10Clock, Reset, and Power C
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Clock, Reset, and Power Controlfami
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Clock, Reset, and Power Control10.2
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control2. F
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Clock, Reset, and Power ControlNote
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Clock, Reset, and Power ControlAfte
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Clock, Reset, and Power Control—
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Clock, Reset, and Power ControlTo p
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Clock, Reset, and Power ControlATBI
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Clock, Reset, and Power Control7. P
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Chapter 11Design for TestThis chapt
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Design for Test11.1.2 MBIST registe
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Design for Testdseed[3:0]Write the
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Design for TestNoteOnly arrays with
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Design for Test• read and write l
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Design for TestTable 11-10 Selectin
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Design for TestArrayFail[22:0] fail
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Design for TestCLKARESETnMBISTMODEM
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Design for TestTable 11-19 shows th
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Design for Test11.2 ATPG test featu
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Chapter 12DebugThis chapter describ
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Debug12.1.3 Debug targetThe debug t
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DebugWhen execution of a monitor ta
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DebugTable 12-3 Debug memory-mapped
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Debug12.3.6 Power domains and debug
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DebugLocks permissionYou can lock t
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DebugTable 12-6 shows the behavior
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Debug12.4 Debug register descriptio
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DebugThe Debug Self Address Offset
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DebugBits Field FunctionTable 12-14
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DebugBits Field Function[9] - Reser
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DebugThe DTR access mode can be one
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DebugBitsFieldFunctionTable 12-16 s
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DebugTable 12-17 Vector Catch Regis
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Debug31 3 2 1 0ReservedNot write-th
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Debug12.4.16 Watchpoint Control Reg
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DebugTable 12-32 Management registe
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DebugTable 12-44 Peripheral Identif
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Debug12.8.4 Writing to the CPSR in
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DebugTable 12-58 Values to write to
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Chapter 13NEON and VFP Programmer
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NEON and VFP Programmer’s Modelre
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AC Characteristicsb. Figure 10-6 on
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Appendix ASignal DescriptionsThis a
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Signal DescriptionsA.2 ATB interfac
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Signal DescriptionsTable A-3 MBIST
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Signal DescriptionsA.4 Preload engi
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GlossaryThis glossary describes som
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GlossaryDouble-precision valueConsi
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Glossary• arithmetic operation re
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GlossarySetSet-associative cacheSee
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GlossaryTrapTrigger instructionAn e
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GlossaryWrite-back (WB)Write buffer
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