Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorBits Field Security State FunctionTable 3-49 Auxiliary Control Register bit functions (continued)NSS[9] PLDNOP R R/W Executes PLDinstructions as a NOP instruction:0 = PLD instructions behave as defined in the ARM ArchitectureReference Manual, reset value1 = PLD instructions are executed as NOP instructions.The PLD instruction acts as a hint to the memory system. If thePLDNOP is set to 0, the processor performs a memory accessfor the PLD instruction. If the PLDNOP is set to 1, the processordoes not perform a memory access. See the ARM ArchitectureReference Manual for more information on the PLD instruction.[8] WFINOP R R/W Executes WFI instructions as a NOP instruction:0 = executes WFI instructions as defined in the ARMArchitecture Reference Manual, reset value1 = executes WFI instructions as NOP instruction.The WFI instruction places the processor in a low-power stateand stops it from executing any more until an interrupt or adebug request occurs. If the WFINOP is set to 0, then the WFIinstruction places the processor in a low-power state. If theWFINOP is set to 1, the WFI instruction is executed as a NOP anddoes not place the processor in a low-power state. See the ARMArchitecture Reference Manual for more information on theWFI instruction.[7] Disable branch sizemispredictsR R/W Prevents BTB branch size mispredicts:0 = enables BTB branch size mispredicts, reset value1 = executes the CP15 Invalidate All and Invalidate by MVAinstructions as specified and prevents BTB branch sizemispredicts.[6] IBE R R/W Invalidates BTB enable:0 = executes the CP15 Invalidate All and Invalidate by MVAinstructions as a NOP instruction, reset value1 = executes the CP15 Invalidate All and Invalidate by MVAinstructions as specified.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-65