Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power Control10.2 Reset domainsSimilar to the multiple clock domains within the processor, there are multiple resetdomains:• Power-on reset• Soft reset on page 10-7• APB and ATB reset on page 10-8• Hardware RAM array reset on page 10-8• Reset of memory arrays on page 10-9.All resets are active-LOW inputs, and each reset can affect one or more clock domains.Table 10-1 shows the different resets and what areas of the processor are controlled bythose resets.Table 10-1 Reset inputsSignalCore(CLK)NEON (CLK)ETM(CLK)Debug(CLK)APB(PCLK)ATB(ATCLK)nPORESET Reset Reset Reset Reset - -ARESETn Reset Reset - - - -PRESETn - - Reset Reset Reset -ARESETNEONn - Reset - - - -ATRESETn - - - - - ResetNote• There are specific requirements that must be met to reset each clock domainwithin the processor. Not adhering to these requirements can lead to a clockdomain that is not functional.• The documented reset sequences are the only reset sequences validated. Anydeviation from the documented reset sequences might cause an improper reset ofthe clock domain.10.2.1 Power-on resetThe power-on reset sequence is the most critical to the device because logic in all clockdomains must be placed in a benign state following the deassertion of the resetsequence. Figure 10-6 on page 10-6 shows the power-on reset sequence.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 10-5