Cortex-A8 R2P2.pdf - ARM Information Center

AC Characteristics17.3 ATB and CTI interfacesTable 17-3 shows the setup and hold times for:• the ATB interface• the CTI.Table 17-3 Timing parameters of ATB and CTI interfacesSignalClockSetupparameterPercent ofclock periodHoldparameterAFREADYM ATCLK T ovafreadym 30% T ohafreadymAFVALIDM ATCLK T isafvalidm 30% T ihafvalidmASICCTL[7:0] CLK T ovasicctl 30% T ohasicctlATRESETn a,bATCLK - - -ATCLKEN ATCLK T isatclken 30% T ihatclkenATREADYM ATCLK T isatreadym 30% T ihatreadymATBYTESM[1:0] ATCLK T ovatbytesm 30% T ohatbytesmATDATAM[31:0] ATCLK T ovatdatam 30% T ohatdatamATIDM[6:0] ATCLK T ovatidm 30% T ohatidmATVALIDM ATCLK T ovatvalidm 30% T ohatvalidmTRIGGER ATCLK T ovtrigger 30% T ohtriggerCTICHOUT[3:0] ATCLK T ovctichout 30% T ohctichoutCTICHIN[3:0] ATCLK - - -nCTIIRQ a CLK T ovnctiirq 30% T ohnctiirqa. This signal has multiple end-points and must be treated as level-sensitive.b. Figure 10-6 on page 10-6 shows how this signal must be set up.17-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E