Cortex-A8 R2P2.pdf - ARM Information Center

Introduction1.3.1 Instruction fetchThe instruction fetch unit predicts the instruction stream, fetches instructions from theL1 instruction cache, and places the fetched instructions into a buffer for consumptionby the decode pipeline. The instruction fetch unit also includes the L1 instruction cache.1.3.2 Instruction decodeThe instruction decode unit decodes and sequences all ARM and Thumb-2 instructionsincluding debug control coprocessor, CP14, instructions and system controlcoprocessor, CP15, instructions. See Chapter 12 Debug for information on the CP14coprocessor and Chapter 3 System Control Coprocessor for information on the CP15coprocessor.The instruction decode unit handles the sequencing of:• exceptions• debug events• reset initialization• Memory Built-In Self Test (MBIST)• wait-for-interrupt• other unusual events.See Chapter 16 Instruction Cycle Timing for more information on how the processorsequences instructions.1.3.3 Instruction executeThe instruction execute unit consists of two symmetric Arithmetic Logical Unit (ALU)pipelines, an address generator for load and store instructions, and the multiply pipeline.The execute pipelines also perform register write back.The instruction execute unit:• executes all integer ALU and multiply operations including flag generation• generates the virtual addresses for loads and stores and the base write-back value,when required• supplies formatted data for stores and also forwards data and flags• processes branches and other changes of instruction stream and evaluatesinstruction condition codes.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 1-5