Cortex-A8 R2P2.pdf - ARM Information Center

External Memory InterfaceLALast AccessTable 9-7 AXI address channel for data transactions for load/store multiplesTransfer Alignment ENR FA L AARADDR[31:0]ARLEN[2:0]ARSIZE[2:0]ARBURST[1:0]ARLOCK[1:0]Noncacheable,or stronglyordered, ordevice LDMsEven word Yes 1 0 [31:3]000 0 64-bit Incr Normal0 0 [31:3]000 0 64-bit Incr Normal0 1 [31:3]000 0 64-bit Incr Normal1 1 [31:3]000 0 64-bit Incr NormalNo 1 0 [31:3]000 0 64-bit Incr Normal0 0 [31:3]000 0 64-bit Incr Normal0 1 [31:3]000 0 64-bit Incr Normal1 1 [31:3]000 0 32-bit Incr NormalOdd word Yes 1 0 [31:2]00 0 32-bit Incr Normal0 0 [31:3]000 0 64-bit Incr Normal0 1 [31:3]000 0 32-bit Incr NormalNo 1 0 [31:2]00 0 32-bit Incr Normal0 0 [31:3]000 0 64-bit Incr Normal0 1 [31:3]000 0 64-bit Incr NormalNoncacheable,or stronglyordered, ordevice STMsEven word Yes 1 0 [31:3]000 0 64-bit Incr Normal0 0 [31:3]000 0 64-bit Incr Normal0 1 [31:3]000 0 64-bit Incr Normal1 1 [31:3]000 0 64-bit Incr NormalNo 1 0 [31:3]000 0 64-bit Incr Normal0 0 [31:3]000 0 64-bit Incr Normal0 1 [31:3]000 0 64-bit Incr Normal1 1 [31:3]000 0 32-bit Incr Normal9-16 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E