Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessora. n is the coprocessor number between 0 and 13.Access to coprocessors in the Nonsecure state depends on the permissions set in the c1,Nonsecure Access Control Register on page 3-73.Attempts to read or write the Coprocessor Access Control Register access bits dependon the corresponding bit for each coprocessor in c1, Nonsecure Access Control Registeron page 3-73. Table 3-52 shows the results of attempted access to coprocessor accessbits for each mode.Table 3-52 Results of access to the Coprocessor Access Control Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserNonsecureAccess ControlRegister bit Read Write Read Write Read Write Read Write0 Data Data b00 Ignored1 Data Data Data DataUndefinedUndefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when thecoprocessor instruction is executed.To access the Coprocessor Access Control Register, read or write CP15 with:MRC p15, 0, , c1, c0, 2 ; Read Coprocessor Access Control RegisterMCR p15, 0, , c1, c0, 2 ; Write Coprocessor Access Control RegisterYou must execute an Instruction Memory Barrier (IMB) sequence immediately after anupdate of the Coprocessor Access Control Register, see Memory Barriers in the ARMArchitecture Reference Manual. You must not attempt to execute any instructions thatare affected by the change of access rights between the IMB sequence and the registerupdate.To determine if any particular coprocessor exists in the system, write the access bits forthe coprocessor of interest with a value other than b00. If the coprocessor does not existin the system the access rights remain set to b00.Note• For the processor, there is a direct relationship between the CPEXIST[13:0]inputs and the Coprocessor Access Control Register bits cp13-cp01.3-68 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E