Cortex-A8 R2P2.pdf - ARM Information Center

Programmer’s ModelWhen the processor executes an IT instruction, it sets these bits according to thecondition in the instruction, and the Then and Else (T and E) parameters in theinstruction. During execution of an IT block, IT[4:0] is shifted:• to reduce the number of instructions to be conditionally executed by one• to move the next bit into position to form the least significant bit of the conditioncode.See the ARM Architecture Reference Manual for more information on the operation ofthe IT execution state bits.2.14.4 The J bitThe J bit in the CPSR indicates when the processor is in ThumbEE state.When T=1:J = 0J = 1The processor is in Thumb state.The processor is in ThumbEE state.Note• You cannot set the J bit to 1 when the T bit is 0. The J bit is written as 0 when theT bit is written as 0.• You cannot use MSR to change the J bit in the CPSR.• The placement of the J bit avoids the status or extension bytes in code running onARMv5TE or earlier processors. This ensures that OS code written using thedeprecated CPSR, SPSR, CPSR_all, or SPSR_all syntax for the destination of anMSR instruction continues to work.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 2-29