Cortex-A8 R2P2.pdf - ARM Information Center

Embedded Trace MacrocellSee the ETM Architecture Specification for more information.Table 14-8 Output signals that can be controlled by the Integration Test RegistersSignal Register Bit DescriptionAFREADYM ITATBCTR0 [1] See ITATBCTR0 Register on page 14-21ATBYTESM[1:0] ITATBCTR0 [9:8] See ITATBCTR0 Register on page 14-21ATDATAM[31, 23, 15, 7, 0] ITATBDATA0 [4:0] See ITATBDATA0 Register on page 14-19ATIDM[6:0] ITATBCTR1 [6:0] See ITATBCTR1 Register on page 14-21ATVALIDM ITATBCTR0 [0] See ITATBCTR0 Register on page 14-21EXTOUT[1:0] ITMISCOUT [9:8] See ITMISCOUT Register on page 14-18TRIGGER ITTRIGGER [0] See ITTRIGGER Register on page 14-19Table 14-9 Input signals that can be read by the Integration Test RegistersSignal Register Bit DescriptionAFVALIDM ITATBCTR2 [1] ITATBCTR2 Register on page 14-20ATREADYM ITATBCTR2 [0] ITATBCTR2 Register on page 14-20DBGACK ITMISCIN [4] ITMISCIN Register on page 14-18EXTIN[3:0] ITMISCIN [3:0] ITMISCIN Register on page 14-18Using the Integration Test RegistersThe CoreSight Design Kit Technical Reference Manual gives a full description of theuse of the Integration Test Registers to check integration. In brief, when bit [0] of theIntegration Mode Control Register is set to 1:• Values written to the write-only Integration Test Registers map onto the specifiedoutputs of ETM. For example, writing 0x3 to ITMISCOUT[1:0] causesEXTOUT[1:0] to take the value 0x3.• Values read from the read-only integration test registers correspond to the valuesof the specified inputs of ETM. For example, if you read ITMISCIN[1:0] youobtain the value of EXTIN.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 14-17