Cortex-A8 R2P2.pdf - ARM Information Center

List of FiguresFigure 12-17 PRCR format ......................................................................................................... 12-50Figure 12-18 PRSR format ......................................................................................................... 12-52Figure 12-19 Integration Internal Output Control Register format .............................................. 12-57Figure 12-20 Integration External Output Control Register format ............................................. 12-58Figure 12-21 Integration Input Status Register format ............................................................... 12-60Figure 12-22 Integration Mode Control Register format ............................................................. 12-61Figure 12-23 Claim Tag Set Register format .............................................................................. 12-62Figure 12-24 Claim Tag Clear Register format ........................................................................... 12-62Figure 12-25 Lock Access Register format ................................................................................ 12-63Figure 12-26 Lock Status Register format .................................................................................. 12-64Figure 12-27 Authentication Status Register format ................................................................... 12-65Figure 12-28 Device Type Register format ................................................................................. 12-66Figure 12-29 Timing of core power-down and power-up sequences ......................................... 12-90Figure 13-1 NEON and VFP register bank ................................................................................. 13-5Figure 13-2 Register banks ........................................................................................................ 13-7Figure 13-3 Floating-Point System ID Register format ............................................................. 13-13Figure 13-4 Floating-Point Status and Control Register format ................................................ 13-15Figure 13-5 Floating-Point Exception Register format .............................................................. 13-18Figure 13-6 MVFR0 Register format ........................................................................................ 13-18Figure 13-7 MVFR1 Register format ........................................................................................ 13-19Figure 14-1 Example CoreSight debug environment ................................................................. 14-4Figure 14-2 ID Register format ................................................................................................. 14-10Figure 14-3 Configuration Code Register format ...................................................................... 14-12Figure 14-4 Configuration Code Extension Register format ..................................................... 14-13Figure 14-5 Mapping between the Component ID Registers and the component ID value ...... 14-16Figure 14-6 ITMISCOUT Register format ................................................................................. 14-18Figure 14-7 ITMISCIN Register format ..................................................................................... 14-18Figure 14-8 ITTRIGGER Register format ................................................................................. 14-19Figure 14-9 ITATBDATA0 Register format ............................................................................... 14-20Figure 14-10 ITATBCTR2 Register format ................................................................................. 14-20Figure 14-11 ITATBCTR1 Register format ................................................................................. 14-21Figure 14-12 ITATBCTR0 Register format ................................................................................. 14-22Figure 15-1 Debug system components ..................................................................................... 15-2Figure 15-2 Cross Trigger Interface channels ............................................................................ 15-4Figure 15-3 Asynchronous to synchronous converter ................................................................ 15-8Figure 15-4 CTI Control Register format .................................................................................. 15-13Figure 15-5 CTI Interrupt Acknowledge Register format .......................................................... 15-13Figure 15-6 CTI Application Trigger Set Register format ......................................................... 15-14Figure 15-7 CTI Application Trigger Clear Register format ...................................................... 15-15Figure 15-8 CTI Application Pulse Register format .................................................................. 15-16Figure 15-9 CTI Trigger to Channel Enable Registers format .................................................. 15-16Figure 15-10 CTI Channel to Trigger Enable Registers format .................................................. 15-17Figure 15-11 CTI Trigger In Status Register format ................................................................... 15-18Figure 15-12 CTI Trigger Out Status Register format ................................................................ 15-19Figure 15-13 CTI Channel In Status Register format ................................................................. 15-19Figure 15-14 CTI Channel Gate Register format ........................................................................ 15-20Figure 15-15 ASIC Control Register format ................................................................................ 15-21ARM DDI 0344E Copyright © 2006-2008 ARM Limited. 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