Cortex-A8 R2P2.pdf - ARM Information Center

Signal DescriptionsA.1 AXI interfaceFor complete descriptions of AXI interface signals, see the AMBA AXI ProtocolSpecification.Table A-1 shows the AXI interface signals that have been added or that have differentdefinitions for the Cortex-A8 processor.Table A-1 AXI interfaceSignalI/OResetDescriptionA64n128 I - Statically selects 64-bit or 128-bit AXI bus width:0 = 128-bit bus width1 = 64-bit bus width.This pin is only sampled during reset of the processor.ACLKEN I - AXI clock gate enable:0 = AXI clock disabled1 = AXI clock enabled.NoteThe rising edge of the internal ACLK signal comes two CLK cycles after theCLK cycle in which ACLKEN is asserted. See Chapter 10 Clock, Reset, andPower Control.ARCACHE[3:0]andAWCACHE[3:0]O Undefined Read or write cache type:b0000 = strongly orderedb0001 = deviceb0010 = reservedb0011 = normal noncacheableb0100 and b0101 = reservedb0110 = cacheable write-through, allocate on reads onlyb0111 = cacheable write-back, allocate on reads onlyb1000 to b1110 = reservedb1111 = cacheable write-back, allocate on both reads and writes.A-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E