Cortex-A8 R2P2.pdf - ARM Information Center

Memory Management Unit6.4 MMU interaction with memory systemYou can enable or disable the MMU as described in the ARM Architecture ReferenceManual.After a CP15 c1 instruction enables the MMU, the processor flushes all followinginstructions in the pipeline. The processor then begins refetching instructions, and theMMU performs virtual-to-physical address mapping according to the translation tabledescriptors in main memory.After a CP15 c1 instruction disables the MMU, the processor flushes all followinginstructions in the pipeline. The processor then begins refetching instructions and usesflat address mapping. In flat address mapping, PA = VA.The following is an example of enabling the MMU:MRC p15, 0, r1, c1, c0, 0 ; read CP15 Register 1ORR r1, r1, #0x1MCR p15, 0, r1, c1, c0, 0 ; enable MMUsFetch translatedFetch translatedFetch translatedFetch translatedThe following is an example of disabling the MMU:MRC p15, 0, r1, c1, c0, 0 ; read CP15 Register 1BIC r1, r1, #0x1MCR p15, 0, r1, c1, c0, 0 ; disabledFetch flatFetch flatFetch flatFetch flatARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 6-5