Cortex-A8 R2P2.pdf - ARM Information Center

DebugBits Field FunctionTable 12-14 shows how the bit values correspond with the Debug Status and ControlRegister functions.[31] - Reserved. RAZ, SBZP.Table 12-14 Debug Status and Control Register bit functions[30] DTRRXfull The DTRRXfull flag:0 = DTRRX empty, reset value1 = DTRRX full.When set to 1, this flag indicates that there is data available in the Receive Data TransferRegister, DTRRX. It is automatically set to 1 on writes to the DTRRX by the debugger, andis cleared to 0 when the processor reads the CP14 DTR. If the flag is not set to 1, the DTRRXreturns an Unpredictable value.[29] DTRTXfull The DTRTXfull flag:0 = DTRTX empty, reset value1 = DTRTX full.When set to 0, this flag indicates that the Transmit Data Transfer Register, DTRTX, is readyfor data write. It is automatically set to 0 on reads of the DTRTX by the debugger, and is setto 1 when the processor writes to the CP14 DTR. If this bit is set to 1 and the core attemptsto write to the DTRTX, the register contents are overwritten and the DTRTXfull flag remainsset.[28] - Reserved. RAZ, SBZP.[27] DTRRXfull_l The latched DTRRXfull flag. This flag is read in one of the following ways:• using CP14 instruction• using the DSCR memory address• using the OSSRR memory address.CP14 instruction returns an Unpredictable value for this bit.DSCR memory address returns the same value as DTRRXfull.OSSRR memory address returns the latched DTRRXfull value, that is, the value ofDTRRXfull that the processor captured on the last DSCR memory address read.If a write to the DTRRX APB address succeeds, DTRRXfull_l is set to 1.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-23