Cortex-A8 R2P2.pdf - ARM Information Center

DebugSVCSMCUndefinedThe processor ignores SVC exceptions.The processor ignores SMC exceptions.When an Undefined Instruction exception occurs in debug state, thebehavior of the core is as follows:• PC, CPSR, SPSR_und, and R14_und are unchanged• the processor remains in debug state• DSCR[8], sticky undefined bit, is set to 1.Precise Data abortWhen a precise Data Abort occurs in debug state, the behavior of the coreis as follows:• PC, CPSR, SPSR_abt, and R14_abt are unchanged• the processor remains in debug state• DSCR[6], sticky precise data abort bit, is set to 1• DFSR and FAR are set to the same values as if the abort hadoccurred in normal state.Imprecise Data AbortWhen an imprecise Data Abort occurs in debug state, the behavior of thecore is as follows, regardless of the setting of the CPSR A bit:• PC, CPSR, SPSR_abt, and R14_abt are unchanged• the processor remains in debug state• DSCR[7], sticky imprecise data abort bit, is set to 1• the imprecise Data Abort does not cause the processor to performan exception entry sequence so DFSR remains unchanged• the processor does not act on this imprecise Data Abort on exitfrom the debug state, that is, the imprecise abort is discarded.Imprecise Data Aborts on entry and exit from debug stateThe processor performs an implicit Data Synchronization Barrier (DSB) operation aspart of the debug state entry sequence. If this operation detects an imprecise Data Abort,the processor records this event and its type as if the CPSR A bit was set to 1. Thepurpose of latching this event is to ensure that it can be taken on exit from debug state.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-85