Cortex-A8 R2P2.pdf - ARM Information Center

Debug12.5 Management registersThe Management registers define the standardized set of registers that is implementedby all CoreSight components. These registers are described in this section.Table 12-32 shows the contents of the Management registers for the debug unit.Table 12-32 Management registersOffsetRegisternumberAccessMnemonicPowerdomainDescription0xD00-0xDFC 832-895 R - Debug Processor Identifier Registers. See ProcessorID Registers on page 12-55.0xE00-0xEF0 854-956 R - - RAZ.0xEF4 957 RW ITCTRL-IOC Core Integration Internal Output Control Register.See Integration Internal Output ControlRegister on page 12-56.0xEF8 958 RW ITCTRL-EOC Core Integration External Output ControlRegister. See Integration External OutputControl Register on page 12-58.0xEFC 959 R ITCTRL-IS Core Integration Input Status Register. SeeIntegration Input Status Register onpage 12-59.0xF00 960 RW ITCTRL Core Integration Mode Control Register. SeeIntegration Mode Control Register onpage 12-61.0xF04-0xF9C 961-999 R - Debug RAZ, reserved for Management Registerexpansion.0xFA0 1000 RW CLAIMSET Debug Claim Tag Set Register. See Claim Tag SetRegister on page 12-61.0xFA4 1001 RW CLAIMCLR Debug Claim Tag Clear Register. See Claim TagClear Register on page 12-62.0xFA8-0xFBC 1002-1003 R - - RAZ.0xFB0 1004 W LOCKACCESS Debug Lock Access Register. See Lock AccessRegister on page 12-63.0xFB4 1005 R LOCKSTATUS Debug Lock Status Register. See Lock StatusRegister on page 12-63.12-54 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E