Cortex-A8 R2P2.pdf - ARM Information Center

GlossaryAXI terminologyThe following AXI terms are general. They apply to both masters and slaves:Active read transactionA transaction for which the read address has transferred, but the last readdata has not yet transferred.Active transferA transfer for which the xVALID 1 handshake has asserted, but for whichxREADY has not yet asserted.Active write transactionA transaction for which the write address or leading write data hastransferred, but the write response has not yet transferred.Completed transferA transfer for which the xVALID/xREADY handshake is complete.PayloadThe non-handshake signals in a transfer.Transaction An entire burst of transfers, comprising an address, one or more datatransfers and a response transfer (writes only).TransmitTransferAn initiator driving the payload and asserting the relevant xVALIDsignal.A single exchange of information. That is, with one xVALID/xREADYhandshake.The following AXI terms are master interface attributes. To obtain optimumperformance, they must be specified for all components with an AXI master interface:Combined issuing capabilityThe maximum number of active transactions that a master interface cangenerate. This is specified instead of write or read issuing capability formaster interfaces that use a combined storage for active write and readtransactions.1. The letter x in the signal name denotes an AXI channel as follows:AW Write address channel.W Write data channel.B Write response channel.AR Read address channel.R Read data channel.Glossary-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E