Cortex-A8 R2P2.pdf - ARM Information Center

Introduction1.8 Product revisionsThis manual is for revision r2p2 of the Cortex-A8 processor. See Product revision statuson page xxviii for details of revision numbering. This section summarizes thedifferences in functionality between the releases of this processor.NoteThe first released version of the Cortex-A8 processor was r1p0.r1p0 - r1p1 The following changes have been made in this release:• Maintenance upgrade to fix errata.• ID Register values changed to reflect r1p1 revision.• The L2EN bit of the Auxiliary Control Register is banked betweenNonsecure and Secure states.• SAFESHIFTRAM top-level pin added for ATPG test.• ETM and NEON configurability support added.r1p1 - r2p0 The following changes have been made in this release:• Maintenance upgrade to fix errata.• ID Register values changed to reflect r2p0 revision.• CLKSTOPREQ and CLKSTOPACK functionality added to stopand restart the processor clocks without relying on software toexecute WFI instruction.• The SAFESHIFTRAM signal is replaced with theSAFESHIFTRAMIF, SAFESHIFTRAMLS, andSAFESHIFTRAML2 signals for ATPG test.• Intelligent Energy Management (IEM) multiple power domainsupport added.• 1-way and 4-way L2 tag bank removed.• 64KB and 2MB L2 cache sizes removed.• ETMPWRDWNREQ and ETMPWRDWNACK are no longerrequired because debug and the ETM use the same power domain.ETMPWRDWNREQ must be tied to 0. See Static or leakagepower management on page 10-14 for information on thesupported Cortex-A8 power domain configurations.1-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E