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Level 1 Memory System7.1 About the L1 memory systemThe L1 memory system consists of separate instruction and data caches in a Harvardarrangement. The L1 memory system provides the core with:• fixed line length of 64 bytes• support for 16KB or 32KB caches• two 32-entry fully associative ARMv7-A MMU• data array with parity for error detection• virtually indexed, physically tagged caches• 4-way set associative cache structure• random replacement policy• nonblocking cache behavior for Advanced SIMD code• blocking for integer code• MBIST• support for hardware reset of the L1 data cache valid RAM, see Hardware RAMarray reset on page 10-8.7-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E
Level 1 Memory System7.2 Cache organizationEach cache is 4-way set associative of configurable size. They are virtually indexed andphysically tagged. The cache sizes are configurable with sizes of 16KB or 32KB. Boththe instruction cache and the data cache are capable of providing two words per cyclefor all requesting sources. Data cache can provide four words per cycle for NEON orVFP memory accesses.The system control coprocessor, CP15, handles the control of the L1 memory systemand the associated functionality, together with other system wide control attributes. SeeChapter 3 System Control Coprocessor for more information on CP15 registers.7.2.1 Cache control operationsThe cache control operations that are supported by the processor are described inChapter 3 System Control Coprocessor.7.2.2 Cache miss handlingA cache miss results when a read access is not present in the cache. The caches performcritical word-first cache refilling.7.2.3 Cache disabled behaviorIf you disable the cache then the cache is not accessed for reads or writes. This ensuresthat you can achieve maximum power savings. It is therefore important that before youdisable the cache, all of the entries are cleaned to ensure that the external memory hasbeen updated. In addition, if the cache is enabled with valid entries in it then it ispossible that the entries in the cache contain old data. Therefore the cache must becompletely cleaned and invalidated before being disabled. Unlike normal reads andwrites to the cache, cache maintenance operations are performed even if the cache isdisabled.7.2.4 Unexpected hit behaviorAn unexpected hit is where the cache reports a hit on a memory location that is markedas noncacheable or shared. The unexpected hit is ignored.For writes, an unexpected cache hit does not result in the cache being updated.7.2.5 Cache parity error detectionThe purpose of cache parity error detection is to increase the tolerance to memory faults.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 7-3
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Cortex -A8Revision: r2p2Technical R
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Product StatusThe information in th
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ContentsCortex-A8 Technical Referen
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Contents7.8 Parity detection ......
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ContentsA.2 ATB interface .........
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List of TablesCortex-A8 Technical R
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List of TablesTable 3-103 Results o
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List of TablesTable 12-1 Access to
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List of TablesTable 15-3 CTI regist
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List of Tablesxx Copyright © 2006-
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List of FiguresFigure 3-10 Memory M
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List of FiguresFigure 10-13 Retenti
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List of FiguresFigure 15-16 CTI Cha
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PrefaceAbout this manualThis is the
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PrefaceChapter 16 Instruction Cycle
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PrefacePrefix CPrefix HPrefix nPref
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the processor
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Introduction1.3 Components of the p
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Introduction1.3.4 Load/storeThe loa
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Introduction1.4 External interfaces
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Introduction1.6 Power managementThe
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Introduction1.8 Product revisionsTh
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Introduction1-14 Copyright © 2006-
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Programmer’s Model• Hardware co
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Programmer’s Model2.2 Thumb-2 ins
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Programmer’s Model2.3 ThumbEE ins
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Programmer’s ModelThumbEE Handler
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Programmer’s Model2.4 Jazelle Ext
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Programmer’s Model— the registe
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Programmer’s ModelNonsecureSecure
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Programmer’s Model2.7 VFPv3 archi
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Programmer’s Model2.9 Data typesT
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Programmer’s ModelBitHigher addre
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Programmer’s Model2.12 Operating
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Programmer’s ModelIn privileged m
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Programmer’s Model16 generalpurpo
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Programmer’s ModelIn ARM state, y
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Programmer’s Model2.14.5 The GE[3
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Programmer’s ModelT bitThe T bit
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Programmer’s ModelOnly secure pri
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Programmer’s Model2.15.2 Leaving
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Programmer’s ModelAn internal or
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Programmer’s ModelImprecise data
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
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Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.1.6 Sys
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System Control CoprocessorThe TCM T
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System Control CoprocessorThe Auxil
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System Control Coprocessora. n is t
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System Control CoprocessorMRC p15,
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System Control CoprocessorVA to PA
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System Control CoprocessorInvalidat
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System Control Coprocessorb. The EN
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System Control Coprocessor• acces
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System Control CoprocessorYou can c
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System Control CoprocessorIf the op
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System Control CoprocessorTo access
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System Control Coprocessora. An ent
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System Control CoprocessorTo access
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System Control CoprocessorThe PLE I
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Page 289 and 290: Chapter 5Program Flow PredictionThi
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control2. F
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Clock, Reset, and Power ControlNote
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Clock, Reset, and Power ControlAfte
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control—
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Clock, Reset, and Power ControlThe
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlTo p
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Clock, Reset, and Power ControlATBI
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Clock, Reset, and Power Control7. P
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Chapter 11Design for TestThis chapt
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Design for Test11.1.2 MBIST registe
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Design for Testdseed[3:0]Write the
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Design for TestNoteOnly arrays with
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Design for Test• read and write l
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Design for TestTable 11-10 Selectin
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Design for TestTable 11-15 shows ho
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Design for TestArrayFail[22:0] fail
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Design for TestWhen testing the tag
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Design for TestCLKARESETnMBISTMODEM
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Design for TestNoteNormal MBIST tes
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Design for TestRowmaxmax - 11 1 1 1
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Design for Test2. R, W_, R_, incr.3
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Design for TestRow32100 00 00 00 00
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Design for Test11.2 ATPG test featu
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Design for TestOne methodology for
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Chapter 12DebugThis chapter describ
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DebugTable 12-3 Debug memory-mapped
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Debug12.3.6 Power domains and debug
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DebugThe Debug Self Address Offset
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DebugBits Field FunctionTable 12-14
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DebugBits Field Function[9] - Reser
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DebugThe DTR access mode can be one
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DebugBitsFieldFunctionTable 12-16 s
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DebugTable 12-17 Vector Catch Regis
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DebugTable 12-44 Peripheral Identif
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Debug12.6.5 Watchpoint debug events
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DebugDBGROMADDRThe DBGROMADDR signa
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Debug12.11.1 Debug communications c
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DebugDebugger access to the DCCA de
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DebugTable 12-58 Values to write to
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Chapter 13NEON and VFP Programmer
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NEON and VFP Programmer’s Modelre
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Chapter 14Embedded Trace MacrocellT
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Embedded Trace MacrocellThe followi
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Embedded Trace Macrocell14.8 Instru
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Chapter 15Cross Trigger InterfaceTh
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Cross Trigger Interface• An input
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Cross Trigger InterfaceTable 15-14
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Chapter 16Instruction Cycle TimingT
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Instruction Cycle TimingTable 16-4
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Instruction Cycle Timing16.2.7 Stat
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Instruction Cycle TimingThe number
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Instruction Cycle Timing16.3 Dual-i
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Instruction Cycle TimingReplayevent
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AC Characteristics17.5 L1 and L2 MB
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AC Characteristics17.7 DFT interfac
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AC Characteristicsb. Figure 10-6 on
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Appendix ASignal DescriptionsThis a
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Signal DescriptionsA.2 ATB interfac
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Signal DescriptionsTable A-3 MBIST
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Signal DescriptionsA.4 Preload engi
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Signal DescriptionsTable A-7 Miscel
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Signal DescriptionsA.8 Miscellaneou
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Appendix BInstruction MnemonicsThis
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Instruction MnemonicsTable B-1 Adva
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Instruction MnemonicsB.2 VFP data-p
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GlossaryThis glossary describes som
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GlossaryApplication Specific Integr
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GlossaryRead ID capabilityThe maxim
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GlossaryByte-invariantIn a byte-inv
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GlossaryCAM includes comparison log
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GlossaryDouble-precision valueConsi
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Glossary• arithmetic operation re
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GlossaryInvalidateJazelle architect
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GlossaryPAPenaltyPower-on resetPref
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GlossarySetSet-associative cacheSee
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GlossaryTrapTrigger instructionAn e
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GlossaryWrite-back (WB)Write buffer
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