Cortex-A8 R2P2.pdf - ARM Information Center

Debug31 3 2 1 0ReservedNot write-throughReservedData and unified cache linefillFigure 12-9 Debug State Cache Control Register formatTable 12-19 shows how the bit values correspond with the Debug State Cache ControlRegister functions.Table 12-19 Debug State Cache Control Register bit functionsBits Field Function[31:3] - Reserved. RAZ, SBZP.[2] Not write-through Not write-through:0 = force write-through behavior for regions marked as write-back in debug state, resetvalue1 = normal operation of regions marked as write-back in debug state.[1] - Reserved. RAZ, SBZP.[0] Data and unifiedcache linefillData and unified cache linefill:0 = L1 data cache and L2 cache linefills disabled in debug state, reset value1 = normal operation of L1 data cache and L2 cache in debug state.12.4.11 Instruction Transfer RegisterThe ITR enables the external debugger to feed instructions into the core for executionwhile in debug state. The ITR is a write-only register. Reads from the ITR return anUnpredictable value.Figure 12-10 shows the bit arrangement of the ITR.31 0DataFigure 12-10 ITR formatARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-35