Cortex-A8 R2P2.pdf - ARM Information Center

DebugIf on a power-down request from the processor, the power controller is in emulate mode.It does not remove core or ETM power but, otherwise, it behaves exactly the same as innormal mode.Emulating power down is ideal for debugging applications running on top of operatingsystems that are free of errors because the debug register settings are not lost on apower-down event. However, there are a number of disadvantages such as:• nIRQ and nFIQ interrupts to the processor must be externally masked as part ofthe emulation to prevent them from retiring the WFI instruction from the pipeline.• The reset controller must also be aware of this emulate mode to assert ARESETnon power up, rather than nPORESET. Asserting nPORESET on power up clearsthe debug registers inside the core power domain.• The timing effects of power down and voltage stabilization are not factored in thepower-down emulation. This is the case for systems with voltage recoverycontrolled by a closed loop system that monitors the core supply voltage, ratherthan a fixed timed for voltage recovery.• State lost during power down is not modeled by the emulation, making it possibleto miss errors in the state storage and recovery routines.• Attaching the debugger for a post-mortem debug session is not possible becausesetting the DBGNOPWRDWN signal to 1 might not cause the processor topower up. The effect of setting DBGNOPWRDWN to 1 when the processor isalready powered down is implementation-defined, and is up to the systemdesigner.12.12.3 Detecting power downThe processor enables the debugger to detect a power-down event occurrence so it canattempt to restore the debug session. Power-down events are detected by the followingfeatures:• While the core is powered down, accesses to debug registers return aslave-generated error response. See APB interface on page A-8 and Power downpermission on page 12-14 for more information.• If the processor powers back up again before the debugger had a chance to accessthe APB interface, the debugger can still detect the occurrence of a power-downevent. This is because the sticky power down status bit forces the processor togenerate a slave-generated error response. See Device Power Down and ResetStatus Register on page 12-51 for more details on the sticky power down bit.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-117