Cortex-A8 R2P2.pdf - ARM Information Center

List of FiguresFigure 3-10 Memory Model Feature Register 3 format .............................................................. 3-42Figure 3-11 Instruction Set Attributes Register 0 format ............................................................ 3-43Figure 3-12 Instruction Set Attributes Register 1 format ............................................................ 3-45Figure 3-13 Instruction Set Attributes Register 2 format ............................................................ 3-46Figure 3-14 Instruction Set Attributes Register 3 format ............................................................ 3-48Figure 3-15 Instruction Set Attributes Register 4 format ............................................................ 3-50Figure 3-16 Cache Level ID Register format .............................................................................. 3-52Figure 3-17 Silicon ID Register format ....................................................................................... 3-54Figure 3-18 Cache Size Identification Register format ............................................................... 3-55Figure 3-19 Cache Size Selection Register format .................................................................... 3-57Figure 3-20 Control Register format ........................................................................................... 3-58Figure 3-21 Auxiliary Control Register format ............................................................................ 3-62Figure 3-22 Coprocessor Access Control Register format ......................................................... 3-67Figure 3-23 Secure Configuration Register format .................................................................... 3-69Figure 3-24 Secure Debug Enable Register format ................................................................... 3-72Figure 3-25 Nonsecure Access Control Register format ............................................................ 3-73Figure 3-26 Translation Table Base Register 0 format .............................................................. 3-75Figure 3-27 Translation Table Base Register 1 format .............................................................. 3-77Figure 3-28 Translation Table Base Control Register format ..................................................... 3-79Figure 3-29 Domain Access Control Register format ................................................................. 3-81Figure 3-30 Data Fault Status Register format .......................................................................... 3-83Figure 3-31 Instruction Fault Status Register format ................................................................. 3-85Figure 3-32 c7 format for set and way ....................................................................................... 3-91Figure 3-33 c7 format for MVA ................................................................................................... 3-92Figure 3-34 PA Register format for successful translation ......................................................... 3-94Figure 3-35 PA Register format for unsuccessful translation ..................................................... 3-94Figure 3-36 TLB Operations MVA and ASID format ................................................................ 3-100Figure 3-37 TLB Operations ASID format ................................................................................ 3-101Figure 3-38 Performance Monitor Control Register format ...................................................... 3-101Figure 3-39 Count Enable Set Register format ........................................................................ 3-103Figure 3-40 Count Enable Clear Register format ..................................................................... 3-105Figure 3-41 Overflow Flag Status Register format ................................................................... 3-106Figure 3-42 Software Increment Register format ..................................................................... 3-108Figure 3-43 Performance Counter Selection Register format .................................................. 3-109Figure 3-44 Event Selection Register format ........................................................................... 3-111Figure 3-45 User Enable Register format ................................................................................ 3-118Figure 3-46 Interrupt Enable Set Register format .................................................................... 3-119Figure 3-47 Interrupt Enable Clear Register format ................................................................. 3-120Figure 3-48 L2 Cache Lockdown Register format .................................................................... 3-122Figure 3-49 L2 Cache Auxiliary Control Register format .......................................................... 3-125Figure 3-50 TLB Lockdown Register format ............................................................................ 3-129Figure 3-51 Primary Region Remap Register format ............................................................... 3-133Figure 3-52 Normal Memory Remap Register format .............................................................. 3-134Figure 3-53 PLE identification and Status Registers format .................................................... 3-138Figure 3-54 PLE User Accessibility Register format ................................................................ 3-140Figure 3-55 PLE Channel Number Register format ................................................................. 3-141Figure 3-56 PLE Control Register format ................................................................................. 3-144xxii Copyright © 2006-2008 ARM Limited. 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