Cortex-A8 R2P2.pdf - ARM Information Center

Level 1 Memory SystemTable 7-1 Memory types affecting L1 and L2 cache flows (continued)L1 inner policy aL2 outer policyBuffersflushedDescriptionCacheable,write-back, nowrite-allocateCacheable,write-through, nowrite-allocateNoLoad misses are allocated into L1. L2 makes store hitswrite-through at L2 cache and does not allocate the line intoL2 for store misses.Cacheable,write-through, nowrite-allocateCacheable,write-back, nowrite-allocateNoLoads are allocated into L1. Store hits are made write-throughat L1. Store hits update the cache and are sent to L2. L2 doesnot allocate store misses but they are sent externally.Cacheable,write-through, nowrite-allocateCacheable,write-back,write-allocateNoLoads are allocated into L1. Store hits are made write-throughat L1. Store hits update the cache and are sent to L2. Storemisses are allocated into L2.Cacheable,write-through, nowrite-allocateCacheable,write-through, nowrite-allocateNoLoads are allocated into L1. Store hits are made write-throughat L1. Store hits update the cache and are sent to L2. Storemisses are not allocated into L2.Noncacheable,bufferableNoncacheable,bufferableNoLoads are replayed and access is sent externally. Stores bypassinteger store buffer and are placed into L2 write buffer. Storesare sent externally.a. You can configure the L2 cache to use the inner policy attributes.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 7-7