Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorBits Field Function[31:7] - Reserved. UNP, SBZ.Table 3-79 shows how the bit values correspond with the PAR for an unsuccessfultranslation.Table 3-79 PA Register for unsuccessful translation bit functions[6:1] FSR[12,10,3:0] Holds the FSR bits for the aborted address. See c5, Data Fault Status Register on page 3-82and c5, Auxiliary Fault Status Registers on page 3-87.[0] - Indicates that the translation aborted:1 = translation aborted.Attempts to access the PAR in User mode results in an Undefined Instruction exception.NoteThe VA to PA translation can only generate an abort to the core if the operation failedbecause an external abort occurred on the possible translation table request. In this case,the processor does not update the PA Register. The processor updates the Data FaultStatus Register and the Fault Address Register:• if the EA bit in the Secure Configuration Register is set to 1, the secure versionsof the two registers are updated and the processor traps the abort into Monitormode• if the EA bit in the Secure Configuration Register is not set to 1, the processorupdates the secure or nonsecure versions of the two registers, depends whether thecore is in Secure or Nonsecure state when the operation was issued.For all other cases when the VA to PA operation fails, the processor only updates the PARegister, secure or nonsecure version, depends whether the core is in Secure orNonsecure state when the operation was issued, with the Fault Status Register encodingand bit [0] set to 1. The Data Fault Status Register and Fault Address Register remainunchanged and the processor does not send an abort to the core.To access the PA Register, read or write CP15 c7 with:MRC p15, 0, , c7, c4, 0 ; Read PA RegisterMCR p15, 0, , c7, c4, 0 ; Write PA Register3-96 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E