Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessor3.2.9 c0, Debug Feature Register 0The purpose of Debug Feature Register 0 is to provide information about the debugsystem for the processor.The Debug Feature Register 0 is:• a read-only register common to the Secure and Nonsecure states• accessible in privileged modes only.Figure 3-6 shows the bit arrangement of the Debug Feature Register 0.31 24 23 20 19 16 15 12 11 8 7 4 3 0ReservedMicrocontroller debug model – memory-mappedTrace debug model – memory-mappedTrace debug model – coprocessor-basedCore debug model – memory-mappedSecure debug model – coprocessor-basedCore debug model – coprocessor-basedFigure 3-6 Debug Feature Register 0 formatTable 3-16 shows how the bit values correspond with the Debug Feature Register 0functions.Table 3-16 Debug Feature Register 0 bit functionsBits Field Function[31:24] - Reserved, RAZ.[23:20] Microcontrollerdebug model –memory-mapped[19:16] Trace debug model –memory-mapped[15:12] Trace debug model –coprocessor-basedIndicates support for the microcontroller debug model:0x0 = Processor does not support the microcontroller debugmodel – memory-mapped.Indicates support for the trace debug model – memory-mapped:0x1 = Processor supports the trace debug model – memory-mapped0x0 = Processor does not support the trace debug model – memory-mapped. aIndicates support for the coprocessor-based trace debug model:0x0 = Processor does not support the trace debug model – coprocessor.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-33