Cortex-A8 R2P2.pdf - ARM Information Center

Design for TestL2_config[22:0]Inpttn[5:0]dseed[3:0]L2_ADDR_SCRAMBLE[289:0]rtfailbitmapL2_ram_sel[4:0]L2AdLSB[3:0]L2ValSerL2Rows[11:0]L2TLat[1:0]L2DLat[3:0]Figure 11-2 L2 MBIST Instruction Register bit assignmentsThe pttn[5:0], rtfail, bitmap, and dseed[3:0] fields function the same as in the L1MBIST Instruction Register.L2_ram_sel[4:0]Set bits in the L2_ram_sel[4:0] field to select the L2 RAMs for test as Table 11-6 shows.Table 11-6 Selecting L2 RAMs for test with L2_ram_sel[4:0]BitSelected RAM[0] L2 data RAM low order bits [64:0][1] L2 data RAM high order bits [129:65][2] L2 parity RAM[3] L2 tag RAM[4] L2 valid RAMSetting an L2_ram_sel bit selects the corresponding RAM for test.The MBIST accesses the RAMs serially in the order shown in Table 11-6, except thatthe L2 tag RAM and L2 valid RAM are tested in parallel. You can set the L2ValSer bitto 1 to test these two RAMs serially. See L2ValSer on page 11-12.The reset value of the L2_ram_sel[4:0] field is b11111.L2_config[22:0]The L2_config[22:0] field contains fields for selecting:• read and write latency of the L2 data array11-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E