Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-53 shows how the bit values correspond with the Secure Configuration Registerfunctions.Bits Field Function[31:7] - Reserved. UNP, SBZP.[6] - Reserved, RAZ.Table 3-53 Secure Configuration Register bit functions[5] AW Determines if the A bit in the CPSR can be modified when in the Nonsecure state:0 = disable modification of the A bit in the CPSR in the Nonsecure state, reset value1 = enable modification of the A bit in the CPSR in the Nonsecure state.[4] FW Determines if the F bit in the CPSR can be modified when in the Nonsecure state:0 = disable modification of the F bit in the CPSR in the Nonsecure state, reset value1 = enable modification of the F bit in the CPSR in the Nonsecure state.[3] EA Determines External Abort behavior for Secure and Nonsecure states:0 = branch to abort mode on an External Abort exception, reset value1 = branch to Monitor mode on an External Abort exception.[2] FIQ Determines FIQ behavior for Secure and Nonsecure states:0 = branch to FIQ mode on an FIQ exception, reset value1 = branch to Monitor mode on an FIQ exception.[1] IRQ Determines IRQ behavior for Secure and Nonsecure states:0 = branch to IRQ mode on an IRQ exception, reset value1 = branch to Monitor mode on an IRQ exception.[0] NS bit Defines the operation of the processor:0 = secure, reset value1 = nonsecure.NoteWhen the core runs in Monitor mode the state is considered secure regardless of thestate of the NS bit.3-70 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E