Cortex-A8 R2P2.pdf - ARM Information Center

Design for TestCLKARESETnMBISTMODEMBISTSHIFTMBISTDSHIFTMBISTDATAINMBISTRUNMBISTRESULT[2:0]b110 bxxxxx,dlog[lsb] xx,dlog[msb-1] xx,dlog[msb]Figure 11-10 Timing of MBIST end-of-test datalog retrievalBitmap datalog retrievalFigure 11-11 shows an example of the start of a failure datalog retrieval during bitmapmode. The fail flag remains asserted and no more MBIST testing occurs until theMBISTDSHIFT signal is asserted, which initiates the serial shift-out of the bitmapdatalog. This provides time to switch from fast to slow clocking required for shifting.PLL glitchless switch betweenfast and slow clocking occurs hereCLKMBISTRESULT[1] (fail flag)MBISTDSHIFTMBISTRESULT[0] (data log shift out)D[lsb]MBISTRUNFigure 11-11 Timing of MBIST start of bitmap datalog retrievalFigure 11-12 on page 11-24 shows an example of the end of a failure datalog retrievalduring the execution of a failure bitmap. When all of the bits are shifted out, the PLLswitches back to fast clocking and negates the MBISTDSHIFT signal. This causes theMBIST controller to resume testing.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 11-23