Cortex-A8 R2P2.pdf - ARM Information Center

DebugBits Field FunctionTable 12-14 Debug Status and Control Register bit functions (continued)[21:20] DTR accessmodeDTR access mode. This is a read/write field. You can use this field to optimize DTR trafficbetween a debugger and the processor:b00 = Nonblocking mode, reset valueb01 = Stall modeb10 = Fast modeb11 = reserved.Note• This field only affects the behavior of DSCR, DTR, and ITR accesses through theAPB interface, and not through CP14 debug instructions.• Nonblocking mode is the default setting. Improper use of the other modes might resultin the debug access bus becoming jammed.See DTR access mode on page 12-28 for more information.[19] Discardimpreciseabort[18] a Nonsecurestate status[17] a Secureprivilegednoninvasivedebugdisabled[16] a SecureprivilegedinvasivedebugdisabledDiscard imprecise abort. This read-only bit is set to 1 while the processor is in debug stateand is cleared to 0 on exit from debug state. While this bit is set to 1, the processor does notrecord imprecise Data Aborts. However, the sticky imprecise Data Abort bit is set to 1.0 = imprecise Data Aborts not discarded, reset value1 = imprecise Data Aborts discarded.Nonsecure state status bit:0 = the processor is in Secure state or the processor is in Monitor mode1 = the processor is in Nonsecure state and is not in Monitor mode.Secure privileged noninvasive debug disabled:0 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is HIGH1 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is LOW.This value is the inverse of bit [6] of the Authentication Status Register. See AuthenticationStatus Register on page 12-64.Secure privileged invasive debug disabled:0 = (DBGEN && SPIDEN) is HIGH1 = (DBGEN && SPIDEN) is LOW.This value is the inverse of bit [4] of the Authentication Status Register. See AuthenticationStatus Register on page 12-64.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-25