Cortex-A8 R2P2.pdf - ARM Information Center

Cross Trigger InterfaceTable 15-15 shows how the bit values correspond with the ASIC Control Registerfunctions.Bits Field Function[31:6] - Reserved. RAZ, SBZ.Table 15-15 ASIC Control Register bit functions[5] PMUEXTIN1EDGE Enables edge detection for trigger output 6, PMU CTI event 1.[4] PMUEXTIN0EDGE Enables edge detection for trigger output 5, PMU CTI event 0.[3] ETMEXTIN4EDGE Enables edge detection for trigger output 4, ETM external input 4.[2] ETMEXTIN3EDGE Enables edge detection for trigger output 3, ETM external input 3.[1] ETMEXTIN2EDGE Enables edge detection for trigger output 2, ETM external input 2.[0] ETMEXTIN1EDGE Enables edge detection for trigger output 1, ETM external input 1.You can enable edge detection for each trigger output that is used in the CLK domain.If edge detection is enabled:• a single PMU CTI event is generated for every rising edge of the trigger output• the ETM external input is HIGH for one CLK cycle for every rising edge of thetrigger output.15.6.13 CTI Channel Out Status Register, CTICHOUTSTATUSCTICHOUTSTATUS is a read-only register that provides the status of the CTICTICHOUT outputs.Figure 15-16 shows the bit arrangement of the CTICHOUTSTATUS Register.31 4 3 0ReservedCTICHOUTSTATUSFigure 15-16 CTI Channel Out Status Register format15-22 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E