Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-27 Instruction Set Attributes Register 0 bit functions (continued)Bits Field Function[15:12] Compare and branchinstructionsIndicates support for combined compare and branch instructions:0x1 = Processor supports combined compare and branch instructions.[11:8] Bitfield instructions Indicates support for bitfield instructions:0x1 = Processor supports bitfield instructions.[7:4] Bit countinstructionsIndicates support for bit counting instructions:0x1 = Processor supports CLZ.[3:0] Atomic instructions Indicates support for atomic load and store instructions:0x1 = Processor supports SWP and SWPB.Table 3-28 shows the results of attempted access for each mode.Table 3-28 Results of access to Instruction Set Attributes Register 0 aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Undefined Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.To access the Instruction Set Attributes Register 0, read CP15 with:MRC p15, 0, , c0, c2, 0 ; Read Instruction Set Attributes Register 03.2.16 c0, Instruction Set Attributes Register 1The purpose of the Instruction Set Attributes Register 1 is to provide information aboutthe instruction set that the processor supports beyond the basic set.The Instruction Set Attributes Register 1 is:• a read-only register common to the Secure and Nonsecure states• accessible in privileged modes only.Figure 3-12 on page 3-45 shows the bit arrangement of the Instruction Set AttributesRegister 1.3-44 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E