Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTo access the CNTENC Register, read or write CP15 with:MRC p15, 0, , c9, c12, 2 ; Read CNTENC RegisterMCR p15, 0, , c9, c12, 2 ; Write CNTENC RegisterYou can use the enable, EN, bit [0] of the PMNC Register to disable all performancecounters including CCNT. The CNTENC Register retains its value when the enable bitof the PMNC is set to 0, even though its settings are ignored.3.2.45 c9, Overflow Flag Status RegisterThe purpose of the Overflow Flag Status (FLAG) Register is to enable or disable any ofthe performance monitor counters producing an overflow flag.When reading this register, any overflow flag that reads as 0 indicates the counter hasnot overflowed. Any overflow flag that reads as 1 indicates the counter has overflowed.When writing this register, any overflow flag written with a value of 0 is ignored, thatis, not updated. Any overflow flag written with a value of 1 clears the counter overflowflag to 0.The FLAG Register is:• a read/write register common to Secure and Nonsecure states• accessible as determined by c9, User Enable Register on page 3-117.Figure 3-41 shows the bit arrangement of the FLAG Register.31 304 3 2 1 0CReservedP3P2P1P0Figure 3-41 Overflow Flag Status Register formatTable 3-88 shows how the bit values correspond with the FLAG Register functions.Table 3-88 Overflow Flag Status Register bit functionsBitsFieldFunction[31] C Cycle counter overflow flag.[30:4] - Reserved. UNP, SBZP.[3] P3 Counter 3 overflow flag.3-106 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E