Cortex-A8 R2P2.pdf - ARM Information Center

NEON and VFP Programmer’s ModelTable 13-8 FPSCR Register bit functions (continued)Bits Field Function[15] IDE Input Subnormal exception enable bit[14:13] DNM Do Not Modify[12] IXE Inexact exception enable bit[11] UFE Underflow exception enable bit[10] OFE Overflow exception enable bit[9] DZE Division by Zero exception enable bit[8] IOE Invalid Operation exception enable bit[7] IDC Input Subnormal cumulative flag[6:5] DNM Do Not Modify[4] IXC Inexact cumulative flag[3] UFC Underflow cumulative flag[2] OFC Overflow cumulative flag[1] DZC Division by Zero cumulative flag[0] IOC Invalid Operation cumulative flagVector length and stride controlFPSCR[18:16] is the LEN field and controls the vector length for VFP instructions thatoperate on short vectors. The vector length is the number of iterations in a short vectorinstruction.FPSCR[21:20] is the STRIDE field and controls the vector stride. The vector stride isthe increment value used to select the registers involved in the next iteration of the shortvector instruction.13-16 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E