Cortex-A8 R2P2.pdf - ARM Information Center

Level 1 Memory System7.5 Data cache featuresThis section describes the unique features of the data cache. It contains the following:• Data cache preload instruction• Data cache behavior with C-bit disabled.7.5.1 Data cache preload instructionARMv7-A specifies the PLD instruction as a preload hint instruction. The processor usesthe PLD instruction to preload cache lines to the L2 cache. If the PLD instruction resultsin a L1 cache hit, L2 cache hit, or TLB miss no more action is taken. If a cache miss andTLB hit result, the line is retrieved from external memory and is loaded into the L2memory cache.7.5.2 Data cache behavior with C-bit disabledThe C bit in CP15 Control Register c1 enables or disables the L1 data cache. See c1,Control Register on page 3-58 for more information on caching data when enabling thedata cache. If the C bit is disabled, then memory requests do not access any of the datacache arrays.An exception to this rule is the CP15 data cache operations. If the data cache is disabled,all data cache maintenance operations can still execute normally.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 7-9