Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorBits Field FunctionTable 3-108 shows how the bit values correspond with the L2 Cache Auxiliary ControlRegister functions.[31:30] - Reserved. UNP, SBZP.Table 3-108 L2 Cache Auxiliary Control Register bit functions[29] L2 data RAM readmultiplexer selectConfigures the timing of the read data multiplexer select between one or two cyclesfor all L2 data RAM read operations:0 = two cycles, default1 = one cycle.[28] ECC or Parity Selects ECC or parity:0 = parity1 = ECC.[27] Load data forwardingdisableEnables or disables load data forwarding to any LS or NEON request:0 = enables load data forwarding, default1 = disables load data forwarding.[26] - Reserved. UNP, SBZP.[25] Write combiningdisable[24] Write allocate delaydisable[23] Write allocatecombine disable[22] Write allocatedisableEnables or disables write combining:0 = enables write combine, default1 = disables write combine.Enables or disables external linefill when storing an entire line with write allocatepermission:0 = enables write allocate delay, default1 = disables write allocate delay.Enables or disables combining of data in the L2 write combining buffers:0 = enables write allocate combine, default1 = disables write allocate combine.Enables or disables allocate on write miss in L2:0 = enables write allocate, default1 = disables write allocate.[21] Parity or ECC enable Parity or ECC enable:0 = disables parity or ECC, default1 = enables parity or ECC.[20:17] - Reserved. UNP, SBZP.3-126 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E