Cortex-A8 R2P2.pdf - ARM Information Center

DebugTable 12-24 Meaning of BVR bits [22:20] (continued)BVR[22:20]b100b101b11xMeaningThe corresponding BVR[31:2] and BCR[8:5] are compared against the IVA bus and the state of theprocessor against this BCR. It generates a breakpoint debug event on a joint IVA mismatch and statematch.The corresponding BVR[31:2] and BCR[8:5] are compared against the IVA bus and the state of theprocessor against this BCR. This BRP is linked with the one indicated by BCR[19:16] linked BRP field.It generates a breakpoint debug event on a joint IVA mismatch, state and context ID match.Reserved. The behavior is Unpredictable.12.4.15 Watchpoint Value RegistersThe WVRs are registers 96-111, at offsets 0x180-0x1BC. Each WVR is associated with aWatchpoint Control Register (WCR), for example:• WVR0 with WCR0• WVR1 with WCR1.This pattern continues up to WVR15 with WCR15.A pair of watchpoint registers, WVRn and WCRn, is called a Watchpoint Register Pair(WRPn).The watchpoint value contained in the WVR always corresponds to a Data VirtualAddress (DVA) and can be set either on:• a DVA• a DVA and context ID pair.For a DVA and context ID pair, a WRP and a BRP with context ID comparisoncapability must be linked. A debug event is generated when both the DVA and thecontext ID pair match simultaneously. Table 12-25 shows how the bit values correspondwith the Watchpoint Value Registers functions.Table 12-25 Watchpoint Value Registers bit functionsBitsFieldFunction[31:2] - Watchpoint address[1:0] - Reserved. RAZ, SBZP12-42 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E