Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorTable 3-109 shows the results of attempted access for each mode.Table 3-109 Results of access to the L2 Cache Auxiliary Control Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteData Data Data Undefined Undefined Undefined Undefined Undefineda. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when thecoprocessor instruction is executed.To access the L2 Cache Auxiliary Control Register, read or write CP15 with:MRC p15, 1, , c9, c0, 2 ; Read L2 Cache Auxiliary Control RegisterMCR p15, 1, , c9, c0, 2 ; Write L2 Cache Auxiliary Control RegisterIf you have not configured the processor to include parity and ECC RAM, then softwarecannot set bit [21] to 1, parity or ECC enable bit. The following code sequence showshow to determine if the processor was configured to include parity and ECC RAM.MRC p15, 1, , c9, c0, 2 ; Read L2 Cache Auxiliary Control RegisterORR , , #0x0020_0000; Set parity/ECC enableMCR p15, 1, , c9, c0, 2 ; Write L2 Cache Auxiliary Control RegisterMRC p15, 1, , c9, c0, 2 ; Read L2 Cache Auxiliary Control RegisterTST , #0x0020_0000 ; Test for parity/ECC enableBEQ no_parity_ram_setupparity_ram_setup:;B done_parity_RAM_setupno_parity_ram_setup:;done_parity_RAM_setup:;3.2.56 c10, TLB Lockdown RegistersThe purpose of the TLB Lockdown Registers is to control which of the fully-associativeTLB entries to allocate on the next table walk. The TLB is normally allocated on arotating basis. The oldest entry is always the next allocated.3-128 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E