Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessora. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when thecoprocessor instruction is executed.The current ASID value in the Context ID Register is exported to the MMU.To access the Context ID Register, read or write CP15 with:MRC p15, 0, , c13, c0, 1 ; Read Context ID RegisterMCR p15, 0, , c13, c0, 1 ; Write Context ID RegisterYou must ensure that software executes a Data Synchronization Barrier operationbefore changes to this register. This ensures that all accesses are related to the correctcontext ID.You must execute an IMB instruction immediately after changes to the Context IDRegister. You must not attempt to execute any instructions that are from anASID-dependent memory region between the change to the register and the IMBinstruction. Code that updates the ASID must execute from a global memory region.You must program each process with a unique number to ensure that the ETM anddebug logic can correctly distinguish between processes.3.2.73 c13, Thread and Process ID RegistersThe purpose of the Thread and Process ID Registers is to provide locations to store theIDs of software threads and processes for OS management purposes.The Thread and Process ID Registers are:• three read/write registers banked for Secure and Nonsecure states:— user read/write Thread and Process ID Register— user read-only Thread and Process ID Register— privileged only Thread and Process ID Register.• accessible in different modes:— the user read/write Thread and Process ID Register is read/write in User andprivileged modes— the user read-only Thread and Process ID Register is read-only in Usermode, and read/write in privileged modes— the privileged only Thread and Process ID Register is only accessible inprivileged modes, and is read/write.3-162 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E