Cortex-A8 R2P2.pdf - ARM Information Center

Cross Trigger InterfaceTable 15-18 shows how the bit values correspond with the ITTRIGINACK Registerfunctions.Bits Field FunctionTable 15-18 ITTRIGINACK Register bit functions[31:9] - Reserved, SBZ[8:0] CTTRIGINACK Sets the value of the CTTRIGINACK outputsEach bit of the ITTRIGINACK Register corresponds to a bit on the ITTRIGIN Register.When in integration mode and a trigger input is cleared, you must set the appropriatebit in the ITTRIGINACK Register to 1, to enable the previous trigger input condition tobe acknowledged and cleared. If you do not set the appropriate bit in ITTRIGINACK,the CTI synchronization logic causes the trigger input to continue to be asserted.No bits of the ITTRIGINACK Register are connected to other integration test registersin the processor.15.7.2 ITCHOUT, 0xEE4ITCHOUT is a write-only register. This register controls signal outputs when bit [0] ofthe Integration Mode Control Register is set to 1. Figure 15-18 shows the bitarrangement of the ITCHOUT Register.31 4 3 0ReservedCTCHOUTFigure 15-18 ITCHOUT Register formatTable 15-19 shows how the bit values correspond with the ITCHOUT Registerfunctions.Table 15-19 ITCHOUT Register bit functionsBits Field Function[31:4] - Reserved, SBZ[3:0] CTCHOUT Sets the value of the CTCHOUT outputsARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 15-25