Cortex-A8 R2P2.pdf - ARM Information Center

Clock, Reset, and Power ControlHardware clock stoppingAnother form of architectural clock gating is controlled by the processorCLKSTOPREQ input. Asserting CLKSTOPREQ puts the processor into alow-power state until CLKSTOPREQ is deasserted.Figure 10-10 shows the relationship between CLKSTOPREQ and CLKSTOPACK.Vdd (core)REFCLK(PLL input)CLKSTOPREQCLKSTOPACKCLK> 20 cycles 8 cycles 8 cyclesFigure 10-10 CLKSTOPREQ and CLKSTOPACKWhen the system asserts CLKSTOPREQ, the processor waits for completion of thesame events as in the Wait-For-Interrupt case before entering the low-power state. SeeWait-For-Interrupt architecture on page 10-10 for more information.On entry into the low-power state, the processor asserts the CLKSTOPACK output.Assertion of CLKSTOPACK guarantees that the processor and the AXI interface arein idle state. The APB PCLK domain and the ATB ATCLK clock domain can remainactive.The number of cycles between CLKSTOPREQ and CLKSTOPACK assertion has alower bound of 20 cycles but no upper bound. The upper bound is a function of thelatency to access the slowest device mapped on the processor AXI bus and, therefore,is system-dependent. After the processor asserts CLKSTOPACK, it closes thearchitectural clock gate. However, eight CLK cycles must pass before you can rely onthe architectural clock gate being completely closed.Figure 10-10 shows the system stopping CLK after the architectural clock gate isclosed. This enables additional energy savings, but it is optional. In addition, the supplyvoltage, Vdd (core) can also be lowered as shown in Figure 10-10 to improve energysavings. However, CLK must not stop before the architectural clock gate is closed, thatis, it must continue to run for at least eight cycles after CLKSTOPACK is asserted.10-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E