Cortex-A8 R2P2.pdf - ARM Information Center

System Control CoprocessorMCR p15 0, , c15, c2, 7 ; D-L1 data readMCR p15 0, , c15, c1, 7 ; I-L1 data writeMCR p15 0, , c15, c3, 7 ; I-L1 data readTable 3-155 shows how the bit values correspond with the I-L1 Data 0 Register as aresult of a BTB array read/write operation.Table 3-155 Functional bits of I-L1 Data 0 Register for a BTB array operationBitsFieldFunction[31:0] Data Holds L1 Data 0 Register BTB informationTable 3-156 shows how the bit values correspond with the I-L1 Data 1 Register as aresult of a BTB array read/write operation.Table 3-156 Functional bits of I-L1 Data 1 Register for a BTB array operationBitsFieldFunction[31:28] - Reserved. UNP, SBZ.[27:0] Data Holds L1 Data 1 Register BTB information.To perform a BTB operation on the Data 0 or Data 1 Register, read or write CP15 with:MCR p15 0, , c15, c5, 3 ; I-L1 BTB writeMCR p15 0, , c15, c7, 3 ; I-L1 BTB readTable 3-157 shows how the bit values correspond with the I-L1 Data 0 Register as aresult of a GHB array read/write operation.Table 3-157 Functional bits of I-L1 Data 0 Register for a GHB array operationBitsFieldFunction[31:0] Data Holds L1 Data 0 Register GHB informationTo perform a GHB operation on the Data 0 Register, read or write CP15 with:MCR p15 0, , c15, c5, 2 ; I-L1 GHB writeMCR p15 0, , c15, c7, 2 ; I-L1 GHB read3-168 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E