Cortex-A8 R2P2.pdf - ARM Information Center

DebugDBGROMADDRThe DBGROMADDR signal specifies bits [31:12] of the debug ROM physicaladdress. This is a configuration input and must be tied off or changed while theprocessor is in reset. In a system with multiple debug ROMs, this address must be tiedoff to point to the top-level ROM address.DBGROMADDRV is the valid signal for DBGROMADDR. If the address cannot bedetermined, DBGROMADDR must be tied off to zero and DBGROMADDRV mustbe tied LOW.DBGSELFADDRThe DBGSELFADDR signal specifies bits [31:12] of the offset of the debug ROMphysical address to the physical address where the APB interface is mapped to the baseof the 4KB debug register map. This is a configuration input and must be tied off orchanged while the processor is in reset.DBGSELFADDRV is the valid signal for DBGSELFADDR. If the offset cannot bedetermined, DBGSELFADDR must be tied off to zero and DBGSELFADDRV mustbe tied LOW.12.10.2 Authentication signalsTable 12-57 shows a list of the valid combination of authentication signals along withits associated debug permissions. Authentication signals are used to configure theprocessor so its activity can only be debugged or traced in a certain subset of processormodes and security states.Table 12-57 Authentication signal restrictionsSPIDEN DBGEN a SPNIDEN NIDENSecureinvasivedebugpermittedNonsecureinvasivedebugpermittedSecurenoninvasivedebugpermittedNonsecurenoninvasivedebugpermitted0 0 0 0 No No No No0 0 0 1 No No No Yes0 0 1 0 No No No No0 0 1 1 No No Yes Yes0 1 0 0 No Yes No Yes0 1 0 1 No Yes No YesARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-91