Cortex-A8 R2P2.pdf - ARM Information Center

System Control Coprocessor3.2.24 c0, Cache Size Selection RegisterThe purpose of the Cache Size Selection Register is to hold the value that the processoruses to select which Cache Size Identification Register to use.The Cache Size Selection Register is:• a read/write register banked for Secure and Nonsecure states• accessible in privileged modes only.Figure 3-19 shows the bit arrangement of the Cache Size Selection Register.314 3 1 0ReservedLevelInDFigure 3-19 Cache Size Selection Register formatTable 3-44 shows how the bit values correspond with the Cache Size Selection Registerfunctions.Table 3-44 Cache Size Selection Register bit functionsBitsFieldFunction[31:4] - Reserved. UNP, SBZ.[3:1] Level Cache level selected3'b000 = level 13'b001 = level 23'b010 - 3'b111 = reserved.[0] InD Instruction (1) or Data/Unified (0).Table 3-45 shows the results of attempted access for each mode.Table 3-45 Results of access to the Cache Size Selection Register aSecure privileged Nonsecure privileged Secure User Nonsecure UserRead Write Read Write Read Write Read WriteSecureDataSecureDataNonsecureDataNonsecureDataUndefined Undefined Undefined UndefinedARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 3-57