Cortex-A8 R2P2.pdf - ARM Information Center

Design for TestWhen testing the tag array, bits [16:15] of this field contain the cache way select bits,and the tag array index value is the least-significant bits of fail_addr. Because thefail_addr[14:11] bits are not used for the tag array, they are always zero. Similar to thedata array, the upper bits of the array index value are not used for lower cache sizes andcan be ignored. Values to these upper bits are supplied by the address scrambleconfiguration.Table 11-17 shows how the cache ways are grouped into two ways of read data sentback from the tag RAMs.Table 11-17 L2 cache way groupingTest sequence number aCache way grouping in read data0 way 1, way 01 way 3, way 22 way 5, way 43 way 7, way 6a. Test sequence number is the order that the MBIST controller accessesthe cache ways.The lower-numbered cache ways are always assigned to bits [22:0] of the read data busfor the current test group. The valid RAM contains two data bits for each of the eightcache ways for a total of 16 bits. To achieve a high test quality, all 16 bits are tested inparallel when testing the first group of cache ways. Because the valid bits are typicallyimplemented as a single 16-bit RAM, testing all cache ways in parallel enables the full16 bits to be accessed each time instead of testing it in slices. This provides greaterflexibility with data backgrounds and can reduce test time if the valid RAM is testedserially after the tag RAM.When testing tag RAMs and valid RAMs in parallel, the valid RAM chip select isdisabled to prevent the valid RAM from being accessed during testing of subsequentgroups of cache ways within the tag array.read_muxThe read_mux bit indicates which half of the 65-bit read produced the first failure:0 Indicates failure in bits [31:0].1 Indicates failure in bits [64:32].ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 11-17