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DebugBits Field Function[31:3] - RAZ.Table 12-28 shows how the bit values correspond with the OS Lock Status Registerfunctions.Table 12-28 OS Lock Status Register bit functions[2] 32-bit access Indicates that a 32-bit access is required to write the key to the OS Lock AccessRegister. This bit always reads 0.[1] Lock bit Locked bit:0 = lock is not set1 = lock is set.Writes are ignored. On Present, this bit initializes to the value ofDBGOSLOCKINIT, that is, the OS lock is set if DBGOSLOCKINIT is HIGH.[0] Lock implemented bit Lock implemented bit. It indicates that the OS lock functionality is implemented. Thisbit always reads 1.12.4.19 Operating System Save and Restore RegisterThe OSSRR is a 32-bit read/write register that enables an operating system to save(prior to power-up) or restore (after power-down) those debug registers that reside onthe core power domain while the OS lock is set.Figure 12-16 shows the bit arrangement of the OSSRR.31 0OS save and restoreFigure 12-16 OS Save and Restore Register format12-48 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E
DebugBits Field FunctionTable 12-29 shows how the bit values correspond with the OS Save and RestoreRegister functions.Table 12-29 OS Save and Restore Register bit functions[31:0] OS save andrestoreOS save and restore. A sequence of reads from this register returns the contents of all theregisters that can be saved. A sequence of writes restores the saved values. The OS must initiatethe sequence by writing a 0xC5ACCE55 key to the OSLAR to set the internal pointer to the startingvalue. This is followed by a read from the OSSRR, and then followed by a series of reads orwrites. The first OSSRR read returns the length of the rest of the sequence, that is, the numberof registers to be saved or restored.These registers are saved and restored in the following order:1. WCR12. WCR03. WVR14. WVR05. BCR56. BCR47. BCR38. BCR29. BCR110. BCR011. BVR512. BVR413. BVR314. BVR215. BVR116. BVR017. DTRTX18. DSCR19. DTRRX20. DSCCR21. VCR22. WFAR.Note• If the OS issues a write to the OSSRR after the sequence has been initialized bywriting the key to the OSLAR, the behavior is Unpredictable.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-49
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Cortex -A8Revision: r2p2Technical R
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Product StatusThe information in th
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ContentsCortex-A8 Technical Referen
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Contents7.8 Parity detection ......
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ContentsA.2 ATB interface .........
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List of TablesCortex-A8 Technical R
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List of TablesTable 3-103 Results o
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List of TablesTable 12-1 Access to
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List of TablesTable 15-3 CTI regist
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List of Tablesxx Copyright © 2006-
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List of FiguresFigure 3-10 Memory M
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List of FiguresFigure 10-13 Retenti
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List of FiguresFigure 15-16 CTI Cha
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PrefaceAbout this manualThis is the
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PrefaceChapter 16 Instruction Cycle
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PrefacePrefix CPrefix HPrefix nPref
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the processor
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Introduction1.3 Components of the p
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Introduction1.3.4 Load/storeThe loa
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Introduction1.4 External interfaces
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Introduction1.6 Power managementThe
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Introduction1.8 Product revisionsTh
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Introduction1-14 Copyright © 2006-
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Programmer’s Model• Hardware co
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Programmer’s Model2.2 Thumb-2 ins
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Programmer’s Model2.3 ThumbEE ins
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Programmer’s ModelThumbEE Handler
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Programmer’s Model2.4 Jazelle Ext
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Programmer’s Model— the registe
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Programmer’s ModelNonsecureSecure
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Programmer’s Model2.7 VFPv3 archi
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Programmer’s Model2.9 Data typesT
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Programmer’s ModelBitHigher addre
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Programmer’s Model2.12 Operating
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Programmer’s ModelIn privileged m
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Programmer’s Model16 generalpurpo
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Programmer’s ModelIn ARM state, y
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Programmer’s Model2.14.5 The GE[3
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Programmer’s ModelT bitThe T bit
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Programmer’s ModelOnly secure pri
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Programmer’s Model2.15.2 Leaving
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Programmer’s ModelAn internal or
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Programmer’s ModelImprecise data
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Programmer’s ModelNoteIf the Embe
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Programmer’s Model2.16 Software c
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Programmer’s Model2.17.2 Security
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Programmer’s Model2.18 Control co
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System Control Coprocessor3.1 About
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System Control CoprocessorTable 3-1
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System Control CoprocessorSecurity
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System Control Coprocessor3.1.6 Sys
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System Control CoprocessorThe TCM T
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System Control CoprocessorFigure 3-
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System Control Coprocessor31 28 27
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System Control Coprocessor3.2.20 c0
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System Control Coprocessora. An ent
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System Control CoprocessorThe Auxil
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System Control CoprocessorBits Fiel
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System Control Coprocessora. n is t
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System Control CoprocessorMRC p15,
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System Control CoprocessorVA to PA
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System Control CoprocessorInvalidat
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System Control CoprocessorThe PMNC
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System Control CoprocessorCWhen wri
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System Control Coprocessorb. The EN
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System Control CoprocessorCWhen rea
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System Control Coprocessor• acces
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System Control CoprocessorYou can c
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System Control CoprocessorIf the op
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System Control CoprocessorTo access
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System Control Coprocessora. An ent
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System Control CoprocessorTo access
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System Control CoprocessorThe PLE I
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System Control CoprocessorTo perfor
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System Control CoprocessorLDR R1, =
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System Control CoprocessorLDR R1, =
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System Control CoprocessorL1 Data 0
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System Control CoprocessorInstructi
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System Control CoprocessorParity/EC
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System Control CoprocessorL2 parity
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System Control CoprocessorThe L2 da
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Chapter 4Unaligned Data and Mixed-e
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Unaligned Data and Mixed-endian Dat
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Unaligned Data and Mixed-endian Dat
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Chapter 5Program Flow PredictionThi
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Program Flow Prediction5.2 Predicte
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Program Flow Prediction5.2.1 Return
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Program Flow Prediction5.4 Guidelin
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Program Flow Prediction5.6 Operatin
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Chapter 6Memory Management UnitThis
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Memory Management Unit6.2 Memory ac
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Memory Management Unit6.4 MMU inter
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Memory Management Unit6.6 TLB lockd
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Chapter 7Level 1 Memory SystemThis
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Level 1 Memory System7.2 Cache orga
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Level 1 Memory System7.3 Memory att
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Level 1 Memory SystemTable 7-1 Memo
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Level 1 Memory System7.5 Data cache
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Level 1 Memory SystemAn exception t
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Level 1 Memory System7.8 Parity det
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Chapter 8Level 2 Memory SystemThis
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Level 2 Memory System8.2 Cache orga
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Level 2 Memory System8.3 Enabling a
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Level 2 Memory SystemControl Regist
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Level 2 Memory System8.4.4 Memory r
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Level 2 Memory System8.5 Synchroniz
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Level 2 Memory System8.6 Locked acc
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Chapter 9External Memory InterfaceT
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External Memory Interfaceto the wri
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External Memory InterfaceTable 9-2
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External Memory Interface9.3 AXI in
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External Memory InterfaceBWBCNoTTSS
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Chapter 10Clock, Reset, and Power C
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Clock, Reset, and Power Controlfami
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Clock, Reset, and Power Control10.2
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control2. F
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Clock, Reset, and Power ControlNote
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Clock, Reset, and Power ControlAfte
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Clock, Reset, and Power Control•
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Clock, Reset, and Power Control—
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Clock, Reset, and Power ControlThe
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlTo p
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Clock, Reset, and Power ControlPowe
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Clock, Reset, and Power ControlATBI
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Clock, Reset, and Power Control7. P
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Chapter 11Design for TestThis chapt
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Design for Test11.1.2 MBIST registe
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Design for Testdseed[3:0]Write the
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Design for TestNoteOnly arrays with
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Design for Test• read and write l
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Design for TestTable 11-10 Selectin
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Design for TestTable 11-15 shows ho
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Design for TestArrayFail[22:0] fail
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Design for TestWhen testing the tag
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Design for Test• Bitmap test mode
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Design for TestCLKARESETnMBISTMODEM
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Design for TestCLKARESETnMBISTMODEM
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Design for TestTable 11-19 shows th
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Design for TestNoteNormal MBIST tes
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Design for TestRowmaxmax - 11 1 1 1
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Design for Test2. R, W_, R_, incr.3
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Design for TestRow3210Addressingdir
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Design for TestRow32100 00 00 00 00
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Design for Test11.2 ATPG test featu
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DebugTable 12-58 Values to write to
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Debug}when 1:byte_address_select :=
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DebugNoteIn Example 12-10 on page 1
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Debug12.11.5 Debug state exitWhen e
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DebugExample 12-15 Reading the PCRe
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DebugExample 12-19 Checking for an
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Debug}dscr := ReadDebugRegister(34)
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Debug}scr := (scr | 1);WriteCPReg(1
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DebugIf on a power-down request fro
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Debug; Step 2. Loop writing words f
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Chapter 13NEON and VFP Programmer
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NEON and VFP Programmer’s Modelre
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NEON and VFP Programmer’s ModelS0
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NEON and VFP Programmer’s ModelBa
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NEON and VFP Programmer’s ModelFC
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NEON and VFP Programmer’s ModelTa
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NEON and VFP Programmer’s Model31
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NEON and VFP Programmer’s ModelCo
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Chapter 14Embedded Trace MacrocellT
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Embedded Trace Macrocell14.1.2 The
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Embedded Trace Macrocell(DAP) throu
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Embedded Trace MacrocellTable 14-1
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Embedded Trace MacrocellRegister na
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Embedded Trace MacrocellSee the ETM
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Embedded Trace MacrocellThe followi
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Embedded Trace Macrocellcomparator
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Embedded Trace Macrocell14.8 Instru
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Embedded Trace MacrocellWhen a WFI
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Embedded Trace MacrocellYou can use
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Chapter 15Cross Trigger InterfaceTh
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Cross Trigger Interface• An input
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Cross Trigger Interface15.1.2 The c
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Cross Trigger InterfaceTable 15-2 T
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Cross Trigger Interface15.4 About t
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Cross Trigger InterfaceTable 15-3 C
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Cross Trigger Interface15.6 CTI reg
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Cross Trigger InterfaceNoteThe CTII
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Cross Trigger InterfaceBits Field F
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Cross Trigger Interface15.6.9 CTI T
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Cross Trigger InterfaceTable 15-14
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Cross Trigger InterfaceActual Compo
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Chapter 16Instruction Cycle TimingT
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Instruction Cycle Timing16.2 Instru
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Instruction Cycle Timingis availabl
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Instruction Cycle TimingTable 16-4
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Instruction Cycle Timing16.2.7 Stat
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Instruction Cycle TimingThe number
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Instruction Cycle Timing16.3 Dual-i
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Instruction Cycle TimingReplayevent
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Instruction Cycle TimingPredicting
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Instruction Cycle TimingUsing MCR i
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Instruction Cycle TimingExample 16-
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Instruction Cycle Timing16.6.3 Adva
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Instruction Cycle TimingFor example
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AC CharacteristicsThe timing parame
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AC CharacteristicsTable 17-2 Timing
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AC Characteristics17.4 APB interfac
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AC Characteristics17.5 L1 and L2 MB
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AC Characteristics17.7 DFT interfac
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AC Characteristicsb. Figure 10-6 on
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Appendix ASignal DescriptionsThis a
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Signal DescriptionsA.2 ATB interfac
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Signal DescriptionsTable A-3 MBIST
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Signal DescriptionsA.4 Preload engi
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Signal DescriptionsTable A-6 APB in
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Signal DescriptionsTable A-7 Miscel
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Signal DescriptionsA.8 Miscellaneou
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Appendix BInstruction MnemonicsThis
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Instruction MnemonicsTable B-1 Adva
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Instruction MnemonicsB.2 VFP data-p
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GlossaryThis glossary describes som
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GlossaryApplication Specific Integr
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GlossaryRead ID capabilityThe maxim
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GlossaryByte-invariantIn a byte-inv
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GlossaryCAM includes comparison log
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GlossaryDouble-precision valueConsi
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Glossary• arithmetic operation re
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GlossaryInvalidateJazelle architect
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GlossaryPAPenaltyPower-on resetPref
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GlossarySetSet-associative cacheSee
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GlossaryTrapTrigger instructionAn e
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GlossaryWrite-back (WB)Write buffer
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