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Cortex-A8 R2P2.pdf - ARM Information Center

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System Control CoprocessorTable 3-97 Values for predefined events (continued)Value0x710x720x73-0xFFDescriptionCounts any event from external input source PMUEXTIN[1].Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1].Reserved.If this unit generates an interrupt, the processor asserts the pin nPMUIRQ. You canroute this pin to an external interrupt controller for prioritization and masking. This isthe only mechanism that signals this interrupt to the core.The absolute counts recorded might vary because of pipeline effects. This has negligibleeffect except in cases where the counters are enabled for a very short time.In addition to the counters within the processor, most of the events that Table 3-97 onpage 3-112 shows are available to the ETM unit or other external trace hardware toenable the events to be monitored. See Chapter 14 Embedded Trace Macrocell andChapter 15 Cross Trigger Interface for more information.3.2.50 c9, Performance Monitor Count RegistersThere are four Performance Monitor CouNT (PMCNT0-PMCNT3) Registers in theprocessor. The purpose of each PMCNT Register, as selected by the PMNXSELRegister, is to count instances of an event selected by the EVTSEL Register. Bits [31:0]of each PMCNT Register contain an event count.The PMCNT0-PMCNT3 Registers are:• read/write registers common to Secure and Nonsecure states• accessible as determined by c9, User Enable Register on page 3-117.Table 3-98 shows the results of attempted access for each mode.Table 3-98 Results of access to the Performance Monitor Count Registers aSecure privileged Nonsecure privileged Secure User Nonsecure UserEN b Read Write Read Write Read Write Read Write0 Data Data Data Data Undefined Undefined Undefined Undefined1 Data Data Data Data Data Data Data Dataa. An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessorinstruction is executed.3-116 Copyright © 2006-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0344E

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