Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle TimingThe number of cycles required to execute an LDM or STM instruction is (number ofregisters / 2) or 2 cycles, whichever is greater.If register writeback is enabled, it is done in the first iteration in the E2 stage, as it isdone in normal load/store instructions.16.2.10 Branch instructionsAny write to the PC is considered a branch. This section describes both standard Bbranch instructions in addition to different instruction types with the PC as thedestination register. In general, branch instructions schedule very well and have veryfew hazards that prevent superscalar issue. There are several properties to the executionof branches that make them behave differently than other instructions.Conditional branchesConditional branches are executed differently than other conditional instructions. Mostconditional instructions take the destination register as an additional source and thecondition codes are resolved in E2. Branches do not require the destination register, PC,as an additional source because they already use the PC as a source. They are alsodifferent than normal conditional operations because the flags resolve the conditioncodes in E3 rather than E2. This enables the pairing of a flag setting instruction and abranch in the same cycle.Branches with the PC as a source or destinationUsing the PC as a source register does not generally result in scheduling hazards as forthe case of a general-purpose register. This is because the PC values are predicted in thepipeline and are readily available to each instruction without any forwarding required.The only exception to this rule is that an instruction with a PC as a source register cannotbe dual issued with an instruction that uses the PC as a destination register.Other than the dual issue restriction, using the PC as a destination register does notresult in a hazard for subsequent instructions for the same reason.Data processing-based branchesData processing branches can have the same data hazards of nonbranch versions ofthese instructions for operands other than the PC.Load-based branchesAn LDR PC or LDM PC instruction behaves like a normal load with the exception that itrequires one additional cycle to execute.ARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 16-11