Cortex-A8 R2P2.pdf - ARM Information Center

DebugNoteThe debugger or debug monitor can program the debug logic to trigger adebug event on clearing of the OS lock.Debugging of the power-up sequenceWhen debugging the OS power-up sequence:• The processor can be identified while the core is powered down.• The internal signal ARESETn can be held on power up. If bit [2]of the PRCR is set to 1, the nondebug logic of the processor is heldin reset on power up. When this bit is set to 1, it enables thedebugger to wait for the power-up event to occur, reprogram thedebug registers, and start execution by clearing this bit to 0.• The EDBGRQ or DRCR[0] halting debug events can be set to 1 atany point in time, even if the core is powered down.• The debugger can set PRCR[2] to 1, wait for the power-up event tooccur, assert EDBGRQ or DRCR[0], and clear the PRCR[2] bit to0 for the processor to enter debug state on executing the firstinstruction. This enables single-stepping of the power-up sequence.When the debugger detects a slave-generated error response, it indicates that one of thefollowing is true:• the debug registers are not available because the core is powered down• the debug registers are not available because the OS locks the APB interface• the debug registers are available but the error response warns that a previouspower-down event cleared them, that is, the sticky power down bit is set to 1.12-120 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E