Cortex-A8 R2P2.pdf - ARM Information Center

Signal DescriptionsA.6 Miscellaneous signalsTable A-7 shows the signals not included in the previous tables.Table A-7 Miscellaneous signalsSignalI/OResetDescriptionnPORESET I - Active-LOW power-on reset input:0 = apply power-on reset1 = do not apply power-on reset.ARESETn I - Active-LOW AXI reset input:0 = apply AXI reset1 = do not apply AXI reset.ARESETNEONn I - Active-LOW NEON reset input:0 = apply NEON reset1 = do not apply NEON reset.SECMONOUTEN I - Security monitor output enable:0 = disables SECMONOUT[86:0]1 = enables SECMONOUT[86:0].This pin is only sampled during reset of the processor.L1RSTDISABLE I - L1 hardware reset disable input:0 = the L1 valid RAM contents are reset by hardware1 = the L1 valid RAM contents are not reset by hardware.L2RSTDISABLE I - L2 hardware reset disable input:0 = the L2 valid RAM contents are reset by hardware1 = the L2 valid RAM contents are not reset by hardware.CLKSTOPREQ I - Clock stop request:0 = do not stop the internal clocks1 = cause the processor to stop the internal clocks and to assert theCLKSTOPACK output.CLKSTOPACK O 0 Clock stop acknowledge:0 = the internal clocks are not stopped1 = the internal clocks are stopped.A-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI 0344E