Cortex-A8 R2P2.pdf - ARM Information Center

DebugNoteThe Data Abort handler checks the DFSR bits to determine if the exception entry wascaused by a Debug exception or other kind of Data Abort exception. If the cause is aDebug exception, the Data Abort handler must branch to the debug monitor. Theaddress of the instruction to restart can be found in the R14_abt register.Table 12-53 shows the values in the Link Register after exceptions. The ARM andThumb columns in this table represent the processor state in which the exceptionoccurred.Table 12-53 Values in Link Register after exceptionsCause of fault ARM Thumb Return address (RA) meaningBreakpoint RA+4 RA+4 Breakpointed instruction addressWatchpoint RA+8 RA+8 Address of the instruction that triggered the watchpoint eventBKPT instruction RA+4 RA+4 BKPT instruction addressVector catch RA+4 RA+4 Vector addressPrefetch Abort RA+4 RA+4 Address of the instruction that the prefetch abort event canceledData Abort RA+8 RA+8 Address of the instruction that the data abort event canceled12.7.1 Effect of debug exceptions on CP15 registers and WFARThe four CP15 registers that record abort information are:• Data Fault Address Register (DFAR)• Instruction Fault Address Register (IFAR)• Instruction Fault Status Register (IFSR)• Data Fault Status Register (DFSR).See Chapter 3 System Control Coprocessor for more information on these registers.If the processor takes a debug exception because of a watchpoint debug event, theprocessor performs the following actions on these registers:• it does not change the IFSR or IFAR• it updates the DFSR with the debug event encoding• it writes an Unpredictable value to the DFARARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 12-75