Cortex-A8 R2P2.pdf - ARM Information Center

Instruction Cycle TimingFor example, VLDM and VSTM transfer of one or two registers require two cycles, three orfour registers require three cycles, five or six registers require four cycles, and 15 or 16registers require nine cycles.VLD and VST element and structure load/store instructions transfer one up to four 64-bitregisters. The number of cycles required to execute a VLD or VST instruction depends onboth the number of registers in the register list and the alignment requirement. Typically,you can reduce the number of cycles if you use a stronger alignment. For example, a2-register VLD2.16@64 requires two cycles but VLD2.16@128 requires only onecycle.Table 16-20 shows the operation of the Advanced SIMD load/store instructions.Table 16-20 Advanced SIMD load/store instructionsInstructionRegister list(alignment)CyclesSourceResult1 2 3 4 1 2VLDR and VSTR register load/store aVLDR Dd, 12---------Dd:N1--VSTR Dd, 12Dd:N1-----------VLD and VST multiple 1-element or 2, 3, 4-element structure bARM DDI 0344E Copyright © 2006-2008 ARM Limited. All rights reserved. 16-33